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eSeminars
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New Test
Requirements for 40/100 GbE Transceivers
Live Webcast – Register at Lightwave
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Charlie Schaffer, SyntheSys Research |
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Pavel Zivny, Tektronix |
March 2, 2010 • 10:00 am PST/1:00 pm EST
Hosted by Lightwave Magazine • Sponsored by SyntheSys,
in association with Tektronix.
Abstract +
- Strong user demand is ahead of the development of the latest high
speed Ethernet standards. Learn about some of the newest physical layer test
requirements for the new 40/100 GbE standard as we give an overview of
measurements and solutions in this rapidly evolving field.
Register and Watch Webcast from
Lightwave |
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Pass USB 3.0 Compliance the First Time
Live Webcast – Register at Test & Measurement World
Presenter: Cynthia Nakatani, SyntheSys Research
Hosted by Test & Measurement World
February 25, 2010 • 10:00 am PST/1:00 pm EST
Abstract +
- Take your understanding of SuperSpeed USB testing to the next
level with this new eSeminar. We will look at the key aspects of transmitter
testing, along with the less well understood topic of receiver compliance, and
the areas that frequently catch out the unwary. Whether you are new to the
topic or consider yourself an expert, benefit from the considerable test
experience we have gained working closely with customers at Compliance
Workshops and in their development labs.
Register and Watch Webcast from T&M W |
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Characterizing an SFP+ Transceiver at the
16x Fibre Channel Rate
On-Demand Webcast – Register at
Lightwave
Speaker: Charlie Schaffer, Marketing Vice President
In association with Tektronix •
Hosted by Lightwave
October 15, 2009 • 10:00 am PST/1:00 pm EST
Abstract +
- Early development efforts for 16x Fibre channel are proceeding ahead
of the completion of the new standard. In anticipation of the new market need, many
transceiver and component vendors are evaluating new and existing designs at the
14.025 Gb/s data rate. We will outline the key performance requirements and
corresponding measurement methods for transmitter and receiver evaluation.
Register and Watch Webcast from
Lightwave |
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克服闭合的眼 – 设计和测量应对信道损耗的预加重和均衡
家: James Zhang
专家职务: Sales Manager, SyntheSys Research, Inc.
Hosted by EDNChina • June 2009
简介 +
- 本次研讨会将会介绍为通过损耗的信道传输的高速串行数据，例如：计算机底板,
线缆以及连接器等预加重和均衡的
必要性。为了克服由频率相关信道损耗导致的码间干扰现象，可以在不同的信号处理节点进行反向传递函数的计算
和应用，从而进行无误码检测。
执行反向传递函数的电路，例如预加重和均衡，包括数字有限脉冲响应(FIR)滤波器，线性有限脉冲响应(FIR) 均衡器
以及判决反馈均衡器 (DFE)。在理论上的滤波器进行说明以后，将会举例说明由阶跃响应或频域网络分析测量方法而
产生优化脉冲响应滤波器。会提到相关测量方法，PCI Express的例子也会被作为标准引用。
迎参加EDNCHINA在线研讨会，注册用户请先登
(See this webcast in English) |
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Why Different Instruments Give You Different
Jitter Answers
On-Demand Webcast – Register at EDN
Speaker: Charlie Schaffer, Marketing Vice President
Hosted by EDN • February 2009
Abstract +
- The fact that lab instruments, whether of different types, or models
within the same type, give frustratingly different measured results for the same target
device is not news to most engineers. Here we explore some underlying reasons why this occurs.
Register and Watch Webcast from EDN |
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Demystifying Receiver Jitter Tolerance Testing
On-Demand Webcast
Speaker: Steve Sekel, Director of Product Management
Originally broadcast by EDN • September 2008
Abstract +
- Although all serial data standards specify a required receiver
jitter tolerance, compliance testing of the link physical layer has generally
ignored the receiver. However as the data rates are increasing, the standards
organizations are realizing that testing only the transmitter and relying on
interoperability test to cover the receiver will not assure data integrity.
Thus, the newer standards are beginning to incorporate receiver jitter tolerance
testing as part of the “gold suite” of required compliance tests. During this
test, a known compliance pattern is sent to the receiver, superimposed with a
calibrated amount of jitter. Many designers who have only dealt with transmitter
testing have questions of what is involved with a receiver test, and how to
set it up correctly.
This seminar fills the knowledge gaps by:
• Explaining receiver testing
• Giving insight into the sometimes complicated “recipe” of jitter sources used
in the test, including random, periodic, duty cycle distortion, and inter-symbol
interference.
• Showing how these jitter sources relate to the interference mechanisms in the real
communication channel.
• Explaining how to properly calibrate the jitter sources to assure accurate testing
to the standards, without overstressing the receiver.
We will also discuss special requirements for testing receivers using spread spectrum
clocking, or when transmitter pre-emphasis equalization is used.
Register and Watch Webcast |
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The Impact of Clock Recovery on Your Serial Data Measurements
On-Demand Webcast
Speaker: Steve Sekel, Director of Product Management
Originally broadcast by EDN • April 2008
Abstract +
- Clock Recovery is an important component in serial data measurements,
whether evaluating the performance of transmitters, receivers or systems. The performance
of clock recovery has a direct impact on accuracy and repeatability of these measurements.
While engineers commonly spend considerable time trying to achieve jitter measurements
which correlate, few consider the contribution of clock recovery performance.
This seminar fills this knowledge gap, providing the engineer with the information needed
to improve measurement integrity. It covers:
• How clock recovery instruments are applied in the test systems, and the parameters
that affect jitter measurements.
• How PLL bandwidth and peaking alter the jitter transfer function through the system, and
how edge density affects the calibration of these.
• The differences between hardware and software PLL implementation.
• The inaccuracies resulting from trigger latency and unmatched data and clock path delay.
Take a big step toward higher accuracy jitter measurements by increasing your understanding
of this key aspect of your measurement system.
Register and Watch Webcast
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Transmitter Jitter Basics: Two Worlds of Test
On-Demand Webcast
Speaker: Charlie Schaffer, Marketing Vice President
Originally broadcast by LIGHTWAVE • January 2008
Abstract +
- While jitter is a familiar measurement in transmitter testing, it
can be defined very differently depending on the context. In this webinar we compare
and contrast the meanings for telecom standards such as SONET/SDH/OTN with those for
enterprise and storage. We explore eye diagram jitter compliance and the different
philosophies behind bathtub jitter and the frequency banded jitter relied on in
other standards. The implications for compliance and troubleshooting are illustrated
with measurement examples.
This seminar fills this knowledge gap, providing the engineer with the information needed
to improve measurement integrity. It covers:
• How clock recovery instruments are applied in the test systems, and the parameters
that affect jitter measurements.
• How PLL bandwidth and peaking alter the jitter transfer function through the system, and
how edge density affects the calibration of these.
• The differences between hardware and software PLL implementation.
• The inaccuracies resulting from trigger latency and unmatched data and clock path delay.
Take a big step toward higher accuracy jitter measurements by increasing your understanding
of this key aspect of your measurement system.
Register and Watch Webcast |
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Pass PCI Express® Physical Layer
Compliance Testing the First Time!
On-Demand Webcast
Speaker: Bent Hessen-Schmidt, Vice President,
Business Development
Originally broadcast by EDN • December 2007
Abstract +
- With the PCIe 2.0 specification, 5.0 GT/s and 2.5 GT/s receiver
testing are emerging as key requirements for chip designers and add-in card vendors.
In this seminar we look at why the requirements have been set the way they have,
and some of the practicalities of making the measurements. We will then look at
key transmitter measurements such as PLL characterization, jitter measurement in
the presence of de-emphasis, de-emphasis ratio, and dual port measurements.
Measured examples of real devices will be used to illustrate the requirements.
• Learn why some key aspects of the standard are the way they are, including
system architecture and the importance of clock distribution.
• Understand the important aspects of transmitter, clock PLL, and receiver testing.
• See practical example measurements of each.
Register and Watch Webcast |
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Combating Closed Eyes – Design & Measurement of
Pre-Emphasis & Equalization for Lossy Channels
On-Demand Webcast
Speaker: Tom Waschura,
Co-founder and Chief Technology Officer
Originally broadcast by EDN • October 2007
Abstract +
- This seminar introduces the need for pre-emphasis
and equalization for high-speed serial communication over lossy channels
such as backplanes, cables and connectors. In order to overcome the
inter-symbol interference caused by frequency dependent channel losses,
inverse transfer functions can be computed and applied at various points
of the signal processing to enable error-free bit detection.
Circuits are described that implement inverse
transfer functions such as pre-emphasis and equalization, and that
include digitally clocked finite impulse response filters, linear finite
impulse response equalizers as well as decision feedback equalizers
(DFE). Following the theoretical filter development, examples are presented
that derive optimized impulse response filter taps from step response
or frequency domain network analysis measurements. Measurements are
discussed and examples are used from standards such as PCI
Express® Generation 2.
Register and Watch Webcast
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