BERTScope S :: Successful Test Solutions

Successful Compliance Test Solutions

FEBRUARY 2007
View this newsletter online: http://www.bertscope.com/News/eNews_Feb07.html
or click here for text-only

 
Welcome to the BERTScope eNewsletter  
We'd like to let you know about information that could be helpful to you in meeting the challenges of signal integrity testing. In this issue you'll find...

Question: How do I get my PCIe product into loopback mode for receiver tolerance testing?

Answer: Well, the BERTScope has the capability to transmit the appropriate TS1 and TS2 training sequences to initiate loopback followed by your desirable test pattern. If your product is a multi-lane device, then you must first either modify the Compliance Baseboard or use a single-lane adapter; our solutions engineers will be happy to tell you how. Did you know that the BERTScope can also automatically step the jitter frequency and amount to search for the maximum jitter that your receiver can tolerate?

If you have a question you'd like answered in our next newsletter, we would love to hear from you. Comments or questions about this newsletter? Contact eNews editor Jill Hagaman:

jill_hagaman@bertscope.com

If you would like to talk with one of our Sales Engineers about how we can help you with your signal integrity needs, please contact us at

+1 (650) 364-1853
or sales@bertscope.com

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SyntheSys Research, Inc.
3475-D Edison Way
Menlo Park, CA 94023

Phone: +1 (650) 364-1853
Fax: +1 (650) 364-5716

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Industry News

“Clock recovery's impact on test and measurement”
Guy Foster :: LIGHTWAVE Magazine, November 2006
       Clock recovery plays a significant role in making accurate test measurements, whether incorporated into the test setup or as part of the device under test.  As most gigabit communication systems are synchronous, the data within them are timed against a common clock.  Whether traveling across inches of circuit board or traversing continents on optical fiber, the relationship between the data and the clock they were timed against can become disturbed.  By extracting clock directly from the data, signal regeneration at the receiver can be achieved correctly.     ›› For the full story …

“Integration technologies for pluggable backplane optical interconnect system”
Alexei L. Glebov, Michael G. Lee, Kishio Yokouchi :: Fujitsu Laboratories of America
First published by SPIE in Optical Engineering, Vol. 46, Iss. 1, 015403 (January 2007)
       This paper presents integration technologies for board-to-board optical interconnect systems. The connector alignment tolerances demonstrate a weak dependence of the coupling efficiency on the axial displacement and a more significant effect of the radial shifts. The results are evaluated using the BERTScope™ analyzer to show that displacement tolerances can be substantially improved, enabling the modules to successfully pass high-speed transmission tests at data rates up to 11 Gbits/s.        ›› For the full story…

How-To Articles

“PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing”
Joan Gibson :: November 2006
       Add-in cards designed for PCI Express require numerous tests to assure inter-operability with different systems.  This document describes testing to verify transmitter compliance with the PCI Express Card Electromechanical Specifications Revision 1.0a and Revision 1.1, and highlights three important areas in compliance testing:
          •  Accurate views for de-emphasis measurements
          •   Edge density requirements for clock recovery
          •   The speed of making mask tests
   ›› For the full story…

Other Great Resources

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Signal Integrity Success in Computer and Storage Applications Technical Brief –  Click here
SAS Receiver Jitter Tolerance Testing –  Click here
Measurement Brief: Introduction to Measurement of Skew, Including Methods for SATA and SAS Transmitter Compliance Testing –  Click here
Serial ATA Gen2 Jitter Tolerance Testing –  Click here
BERTScope™ Stressed Pattern Generator Product Overview –   Click here
Serial ATA Interoperability Program Method of Implementation (MOI) for PHY and TSG Device Certification Tests using the BERTScope by SyntheSys Research, Inc. –  Click here

What's New at SyntheSys Research

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SyntheSys Research, Inc. introduces the new 20+ GHz bandwidth BERTScope “B” family of products for testing from 0.1 to 12.5 Gb/s. Learn more…
SyntheSys Research, Inc. announces the company has entered into an OEM agreement with Tektronix to offer its advanced clock recovery instrument.  Learn more…
SyntheSys Research, Inc. introduces the BERTScope CRJ clock recovery instrument with jitter analysis capability.  Learn more …
SyntheSys Research, Inc. introduces Spread Spectrum Clock and data generation for the BERTScope S Signal Integrity Instrument Family.    Learn more …
SyntheSys Research, Inc. introduces BERTScope Eye Openers for the convenient and easy-to-use conversion of conventional non-return to zero (NRZ) data to de-emphasized data signals.  Learn more …

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