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Option F2:
F2 Jitter Generation
Option J-Map:
Jitter Map
Option PatternVu:
Equalization Processing
Option SF:
Symbol Filtering
Option SLD:
Stressed Live Data
Option XSSC:
Extended SJ and SSC
Option Selection Table

 

BERTScope PLA Phase Lock Loop Analyzer
BERTScope PLA
Automated Jitter Decomposition with
Long Pattern Jitter Triangulation

Option Jitter Map for the BERTScope family adds BER-based jitter decomposition as well as Long Pattern Jitter Triangu­la­tion, which enables jitter separation on long patterns such as PRBS-31.

Long Pattern Jitter Triangulation

Long Pattern Jitter Triangulation Jitter Map can perform jitter decomposition on data patterns of any length, including the 2+ billion-bit-long PRBS-31, provided that it can first run successfully on a shorter data pattern.

Long patterns have long been used to test high speed digital optical communication devices and interfaces. Engineers working with standards such as 10 Gigabit Ethernet (10GbE) (IEEE 802.3ae-2002), OIF-CEI 2.0, SFP+, XFP, and 40 & 100 GbE (IEEE 802.3ba, draft) routinely turn to PRBS-31 for a rigorous test pattern. In addition, standards are moving toward longer patterns, for example 8 GT/s PCI Express® (PCIe) 3.0 (draft) includes PRBS-23 and DisplayPort 5.4 Gb/s (draft) includes PRBS-16.

Features and Benefits of Jitter Map:
The Jitter Map tree delivers detailed information
  • Uses BER measurements and is capable of direct TJ measurements down to
    10-12 BER and beyond
  • Run directly on patterns of length up to PRBS-15, or run in Jitter Triangulation mode on longer patterns.
  • Measurements include TJ, Random Jitter (RJ), Deterministic Jitter (DJ), Bounded Uncorrelated Jitter (BUJ), Data Dependent Jitter (DDJ), Inter-Symbol Interference (ISI), and Duty Cycle Distortion (DCD).
  • Additional jitter measurements support popular standards
    • Data Dependent Pulse Width Shrinkage (DDPWS), a specific method of DDJ measurement, supports 8G Fibre Channel and SFP+ (SFF-8431)
    • Uncorrelated Jitter (UJ) can be used for 8G Fibre Channel, SFP+, and IEEE 802.3aq (10GBASE-LRM) testing
    • Non-ISI is used in DisplayPort
    • F/2* Jitter, which is jitter on every other bit regardless of logic level, is implied in IEEE 802.3ap (10GBASE-KR) and has appeared in drafts of 8 GT/s PCIe 3.0
  • Jitter Map effectively handles crosstalk as well as many other types of stress
  • Operates on signals with minimal eye opening
  • The navigable jitter tree is informative and intuitive

Ordering Information:

Product Code Description
 BSA7500AB Opt-J-MAP Add Jitter Decomposition to BSA 7500A or B
 BSA12500AB Opt-J-MAP Add Jitter Decomposition to BSA 12500A or B
 BSA17500AC Opt-J-MAP Add Jitter Decomposition to BSA 17500A or C
 BSA25000AC Opt-J-MAP Add Jitter Decomposition to BSA 25000A or C
 
Extended warranty and product upgrade options are available.

 
Schedule a BERTScope DemoTo learn more about how BERTScope can meet your testing needs, or to schedule a demonstration in your lab, contact our Sales Engineers.

 

* F/2 and other Subrate Jitter measurements are available up to 11.2 Gb/s on 17500 and 25000 series BERTScopes

 

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